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-- Company: 
-- Engineer:
--
-- Create Date:   20:15:26 01/03/2011
-- Design Name:   
-- Module Name:   C:/ADAM/Test_copro_right.vhd
-- Project Name:  ADAM
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: CORE_RIGHT
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY Test_copro_right IS
END Test_copro_right;
 
ARCHITECTURE behavior OF Test_copro_right IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT CORE_RIGHT
    PORT(
         clk : IN  std_logic;
         shift : IN  std_logic;
         capture : IN  std_logic;
         update : IN  std_logic;
         gwen : IN  std_logic;
         resetn : IN  std_logic;
         tdi : IN  std_logic;
         tdo : OUT  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal clk : std_logic := '0';
   signal shift : std_logic := '0';
   signal capture : std_logic := '0';
   signal update : std_logic := '0';
   signal gwen : std_logic := '0';
   signal resetn : std_logic := '0';
   signal tdi : std_logic := '0';

 	--Outputs
   signal tdo : std_logic;

   -- Clock period definitions
   constant clk_period : time := 10 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: CORE_RIGHT PORT MAP (
          clk => clk,
          shift => shift,
          capture => capture,
          update => update,
          gwen => gwen,
          resetn => resetn,
          tdi => tdi,
          tdo => tdo
        );

   -- Clock process definitions
   clk_process :process
   begin
		clk <= '0';
		wait for clk_period/2;
		clk <= '1';
		wait for clk_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ns.
      resetn <= '0';
		wait for clk_period;
		
		resetn <= '1';
		tdi <= '0';
      shift <= '1';
		gwen <= '1';
		wait for clk_period;	

		tdi <= '1';
		wait for clk_period;	
      
		tdi <= '1';
		wait for clk_period;	
		
		tdi <= '0';
		update <= '1';
		shift <= '0';
		wait for clk_period;	
		
		update <= '0';
		wait for clk_period;
		
		capture <= '1';
		wait for clk_period;
		
		capture <= '0';
		shift <= '1';

      -- insert stimulus here 

      wait;
   end process;

END;
